1. Field of the Invention
The present invention relates to trench DMOS transistors and, more particularly, to a trench DMOS transistor with reduced gate-to-drain capacitance.
2. Description of the Related Art
A metal-oxide-semiconductor (MOS) transistor is a well-known device that has spaced-apart source and drain semiconductor regions which are separated by a channel semiconductor region of the opposite conductive type. The MOS transistor also has an oxide layer that lies over the channel semiconductor region, and a metal gate that touches the oxide layer and lies over the channel semiconductor region. In addition to metal, the gate of a MOS transistor is also commonly formed with doped polysilicon.
A double-diffused MOS (DMOS) transistor is a power transistor that has a large lightly-doped drain semiconductor region that that touches the channel semiconductor region. A trench DMOS transistor, in turn, is a type of DMOS transistor where the spaced-apart source and drain semiconductor regions of the transistor are vertically aligned.
Trench DMOS transistors can be characterized by a figure of merit (FOM), which is equal to the product of the on-state drain-to-source resistance rDS(ON) and the gate-to-drain charge QGD. For a technology with a given FOM, the on-state drain-to-source resistance rDS(ON) can be reduced by increasing the chip size (area).
Increasing the chip size (area), however, also increases the gate-to-drain capacitance CGD which, in turn, causes the gate-to-drain charge QGD to increase. The increase in the gate-to-drain charge QGD offsets the decrease in the on-state drain-to-source resistance rDS(ON) so that the given FOM value remains unchanged.
This represents a trade off scenario for the on-state drain-to-source resistance rDS(ON) and the gate-to-drain charge QGD. The FOM can only be improved (smaller in value) if the on-state drain-to-source resistance rDS(ON) can be reduced without increasing the gate-to-drain charge QGD, or if the gate-to-drain charge QGD can be reduced without increasing the on-state drain-to-source resistance rDS(ON).
The gate-to-drain charge QGD is usually a dominant portion of the switching charge, and directly impacts the efficiency of a DC-DC converter. The gate-to-drain capacitance CGD, which is a non-linear function of the voltage, is commonly known as the Miller capacitance because the gate-to-drain capacitance CGD causes the total dynamic input capacitance of the DMOS transistor to be larger than the total static input capacitance of the DMOS transistor.
In switching applications, the gate-to-drain capacitance CGD limits the maximum switching frequency of the DMOS transistor (i.e., limits how quickly the DMOS transistor can be repeatedly turned on and off). Thus, as the on-state drain-to-source resistance rDS(ON) falls, the gate-to-drain capacitance CGD rises, the gate-to-drain charge QGD rises, and the maximum switching frequency of the DMOS transistor undesirably falls. Thus, there is a need for a trench DMOS transistor that has both a low on-state drain-to-source resistance rDS(ON) and a low gate-to-drain capacitance CGD.